大綱
Besides advanced node of IC fabrication beyond N5, N3, and N2, the 3D stacking IC is another choice for integration of hybrid chiplets with multiple functional applications, especially for mobile devices.
Trend of 3D stacking IC needs to have redistribution layer (RDL) or interposer with trench silicon via (TSV) for reconnecting multi dies, either logic, memory, RF, or sensors within one chip before packaging.  Measurement of TSV wafer for manufactruing is then very critical in high-volume production with high throuput. This topic of speech covers background of 3D stacking IC, Current status of RDL or interposer with TSV, TSV CMP, and TSV measurment. Finally, some applications of 3D stacking ICs are presented and discussed for future developments.

個人經歷

陳炤彰博士1994美國威斯康辛大學麥迪遜分校畢業，國立台灣科技大學特聘教授。
曾擔任台科大機械系系主任及研發處副研發長、2013中美矽晶技術講座教授與台積電公司特聘研究員。
陳博士長期致力研發精密晶圓加工製程與光學元件模造技術，另除專業學術期刊論文發表與期刊審查外，更與半導體與光電晶圓產業緊密結合，協助國內外相關廠商開發先進製程與檢測技術，進行相關產學研合作與技術轉移。

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