臺大光電所所訊

Study of Current Collapse Behaviors of Dual-gate AlGaN/GaN HEMTs on Si

Professor Jian-Jang Huang’s Laboratory

Graduate Institute of Photonics and Optoelectronics, National Taiwan University

臺灣大學光電所黃建璋教授

Surface traps on GaN-based HEMTs (high-electron-mobility transistors) usually result in the increase of channel on-resistance. It becomes worsen when short pulses are applied during high-frequency and high voltage switching. Here we present a dual-gate transistor structure to suppress the dynamic on-resistance increase. The auxiliary gate under a proper fixed voltage is able to induce additional electrons to compensate the channel carrier loss during main gate switching, leading to a lower dynamic on-resistance.

The dual-gate (DG) AlGaN/GaN HEMT is schematically shown in Fig. 1, along with a conventional device for comparisons. The DC electrical properties reveal that the drain current level of the DG-HEMT with G_L-drive (main gate) and G_R-float (auxiliary gate) is slightly higher than that of SG (single gate) -HEMT due to the additional carriers induced by the floating gate. The DG-HEMT with G_R-drive and G_L-float has the smallest current because of the largest gate-source resistance. When a bias voltage is applied on the auxiliary gate, the current level can be adjusted by the additional carriers. Since the auxiliary gate provides an extra source of supplying electrons to the channel that suffers from current collapse, we further studied current collapse phenomenon of the devices by a pulsed stress-measurement approach. The results suggest within the range of auxiliary gate bias, -2 ~ 2 V, a DG device with the main gate drive on G_R and the auxiliary gate voltage of 0 V on G_L has the lowest R_ON, while SG-HEMT is the worst in most of the stress conditions (see Fig. 2 for various drain and gate lag stresses). The improvement using the dual-gate structure is elucidated from the carrier distribution in the channel region as illustrated in Fig. 3. For the case main gate bias applied on G_R and auxiliary bias on G_L, the depleted carriers from the main gate can be quickly supplied by the carrier underneath the auxiliary electrode under a positive drain voltage with a slight negative impact of carriers recombined with traps on both sides of main gate. Finally, we conclude an auxiliary gate biased at 0 V near the source side results in the best suppress of current collapse.

Fig. 1. Cross-sectional epi-structure of (a) a SG-HEMT and (b) a DG-HEMT.

Fig. 2. (a) Comparison of the normalized R_ON at various drain stress voltages, V_{D_OFF}, and auxiliary gate biases.

Fig. 2. (b) Comparison of the normalized R_ON at various gate lag stress conditions.

Fig. 3. Distribution of electrons in the channel under various biases on the main gate and auxiliary gate electrodes. G_R-drive/G_L-bias at (a) off-state and (b) on-state. G_L-drive/G_R-bias at (c) off-state and (d) on-state. Note there may be small amount of donor-like surface traps (not shown) on both sides of G_L and G_R, depending on the bias voltage of the auxiliary gate.

Mobility Enhancement in P-Type SnO Thin-Film Transistors via Ni Incorporation by Co-Sputtering

Professor I-Chun Cheng

Graduate Institute of Photonics and Optoelectronics, National Taiwan University

臺灣大學光電所陳奕君教授

Oxide semiconductors have been considered one of the most promising candidates for flexible electronics applications owing to their low process temperatures and good reliability. However, the low mobility of p-type oxide semiconductors limits the performance of flexible oxide-TFT-based CMOS technology. In this study, p-type SnO_x:Ni thin films were deposited by reactive rf magnetron co-sputtering, a technique compatible with the current industrial semiconductor manufacturing technology, from Sn and Ni targets. As the Ni-gun power increased, the distribution of Ni in the SnO_x:Ni thin film changed from a more uniform dispersion to nanoclusters, resulting in the crystalline phase transition of SnO_x:Ni from α-SnO (110)-dominant polycrystalline to amorphous and then to α-SnO (101)-dominant polycrystalline. A high-mobility inverted-staggered p-type SnO_x:Ni TFT was then fabricated on a glass substrate with a maximum process temperature of 225°C, which is compatible with flexible polymeric substrates. The TFT fabricated at an optimal Ni-gun power of 42 W exhibited an impressive field-effect mobility of 11 cm²V⁻¹s⁻¹ and on current of 35.2 μA per channel width-to-length ratio; these values are comparable to those of a typical n-type oxide TFT. These results should contribute toward flexible oxide-TFT-based CMOS technology. [IEEE Electron Device Letters, vol. 43, No. 2, pp. 228-231, Feb 2022]

Fig. 1. Elemental EDS maps of SnO_x:Ni thin films deposited at Ni-gun powers of (a) 25 and (b) 42 W. (c) High-resolution TEM images and (d) corresponding fast Fourier transformed diffractograms of SnO_x:Ni channels deposited at Ni-gun powers of 0, 25, and 42 W.

Fig. 2. (a)(b) Transfer characteristics of SnOx:Ni TFTs fabricated with various Ni-gun powers. The channel width and length are 40 μm and 20 μm, respectively. (c) Electrical parameters of SnO_x:Ni TFTs under different Ni-gun powers. Transfer characteristics in (d) log scale and (e) linear scale and (f) output characteristics of SnO_x:Ni TFT fabricated with a Ni-gun power of 42 W.