12/06

University of California Santa Barbara

Silicon Evanescent Photonic Integrated Circuits

201 會議室

14:00-16:00

12/22

Prof. Chi H. Lee (李齊湘)

University of Maryland, College Park, U.S.A.

Polymer Photonics

博理館

101 演講廳

16:30-18:30

劉致為教授 (C. W. Liu)

Prof. Liu was born in Taipei, Taiwan, 1963.

He received both the B.S. and M.S. degree in electrical engineering from National Taiwan University in 1985 and 1987, respectively. He received the Ph.D. degree in electrical engineering from Princeton University in 1994.

He was with the department of Electrical Engineering, National Chung-Hsing University in 1994-95. He has joined the Department of Electrical Engineering, National Taiwan University as an associate Professor since 1996. In 2001, he became a full Professor.

Prof. Liu also led a SiGe project in ERSO/ITRI through a special arrangement between NTU and ITRI as a research director with the rank of senior full researcher from 2001 to 2005.

The research in Prof. Chee Wee Liu’s group is based on the SiGe:C and strained Si/high-K/metat gate, including (1) CMOS and Bipolar circuit design using (strained) Si CMOS and Si/SiGe:C HBTs; (2) device modeling and simulation on Strained Si/Ge FET, HBT, and optoelectronics devices; (3) CMOS optoelectronics with detector, emitter and waveguide; (4) material technologies such as SOI, GeOI, SSDOI, smart-cut, buckling quantum wells, nano-mechanics, and strained-SiGe:C; and (5) the rapid thermal processors for RTA, RTO, RTCVD, and wafer bonding. The strained Si/high-K/metal gate is intentionally to bypass the red brick wall on the ITRS roadmap, but the novel applications such as optoelectronics application are also focused. To lower the cost of strained Si technology, special local strain (process strain) technologies are being developed with calibrated process simulation.

1. CMOS Image sensor / Circuit Design and Processing

   • (Strained) Si CMOS and Si/SiGe HBT Design:
     Strained Si device has a speed enhancement of 10-20%. The circuits such as ring oscillator and trans-impedance amplifier (TIA) is being optimized to use the strained Si devices. For pure bipolar, the power amplifer (PA) for 802.11a+b+g is being developed by using low cost SiGe HBTs. The integrated Photodetectors and TIA are being developed.

   • CMOS Image Sensor:
     An image sensor is a device that converts visual image to an electric signal. It is used chiefly in digital cameras and other imaging devices. It is usually an array of charge-coupled devices or CMOS sensors. CMOS sensors have some advantages over CCDs. They can be fabricated using common CMOS methods, which are less costly, and they use less power in operation. Although initially used in less expensive cameras, the quality of CMOS sensors has improved steadily.

2. Strained-Si / Ge FET Process

The superior transport property of Ge can reach high performance target in the future CMOS technology. However, the cost and unstable Germanium oxide make it difficult to replace Si as industry mainstream. Recently, the structure of ultra thin Ge epitaxially directly grown on Si with compressive strain was proposed. The advantages of high mobility, low cost and compatibility with CMOS process are promising in the future technology.

3. Device Modeling and Simulation:

   • Device Modeling:
     BSIM and Mextram models are being developed to take the strain and optical effects into account for RF and high speed digital applications. Strained Si and MOS photodetector modeling are performed in 3-D and SOI simulations.

   • Device Simulation:
     Simulations on heterojunction structure of strained-Si/Ge devices are proposed. Finite element analyses of ISE-TACD and ANSYS are used to simulate Ge FET and MOS LED/GOI detector theoretically.

4. CMOS Optoelectronics (including source, detector, and waveguide):

The LED and photodetectors, and waveguides using available CMOS technology have been our focus since 1996. Now the LED efficiency, circuit integration, and speed are being improved with nanotechnolgy -enhancements such as Ge/SiC/SiGe quantumd dots, surface plasmom, high-K dielectrics, nanoroughness. Extremely small, highly efficient, and VLSI integratable devices are main purpose of this study. The high-K material research is focused on these novel applications as well as gate stacks.

5. Materials:

New SOI, GeOI, SSDOI material using smart cut, wafer bonding, and nano-mechanics are developed for future device applications. New properties of buckled material and nano-strained material are found and will be incorporated to future device design.

6. RTP Equipments:

Beside the well-equipped functions such as RTA, RTO, RTCVD, a new wafer bonding technique is developed, and other novel RTP functions will be installed. The uniformity and throughput is the current research focus.

7. Mechanical Strained TFTs:

Strained-Si technology has been used extensively as the mainstream Si industry. The method to enhance drive current and mobility of TFTs by external mechanical strain is proposed.

8. Optical Commuincation Front-end:

Integrated detector and TIA

9. Optical Interconnect

The machine has the standard MESC interface, and it can be combined with cluster tool. Now it has functions of rapid thermal oxidation, rapid thermal annealing, chemical vapor deposition, and very high vacuum cleaning, and they can be performed in the same machine.

The Si CMOS has market size of ~200B USD in 2004. Without killer applications, it will be difficult to further increase its market size. The display has ~40B USD market size. Si can increase its market size by replacing the current technologies used in the display. The low cost and mature Si technologies can hopefully make LED display to outperform the TFTLCD in the display market. The indirect bandgap of Si and Ge makes the light emission from Si or Ge to be very inefficient (efficiency far less than a percent), and the bandgap of Si and Ge also limits the emission wavelength to infrared region (1.1 to 2 mm). We have tried very hard in the past decade to pump out the visible light from bulk Si by creating the hot electron/hot hole radiative recombination with the photon energy in the visible light range. Note that the switching speed of bulk Si MOS LED was around the order of m second, according to our previous results. This speed is sufficient for display applications. The quantum confinement of Si(Ge) nanocrystallite can have theoretical life time of ns.

The III-V LED (light emitting diode) display is limited by cost and size and only has niche applications of the display market. The direct bandgap engineering and nanocrystallite Ge(Si) can potentially tune the emission wavelength into visible wavelength, and can increase the light emission efficiency to ~10%. The m sec speed of MOSLED is sufficient for display applications. Due to the emission location from the nanocrystllite embedded in the oxide of the MOS LED. The Si wafer is not necessary and a metal-anode/oxide with embedded nanocrystallite /metal-cathode (MIM LED) is proposed to inject carriers from Schottky barriers. This MIM LED can be potentially fabricated on glass substrate with the size comparable with TFTLCD. This technology will enable Si to share the display markets with TFTLCD technology.

v 劉教授對於同學們在學習方面有下列的建議：  

1. 風簷展書讀，古道照顏色。

2. Team work is the most important.